Scaling Compute
Backed by nearly £50m, this programme looks to redefine our current compute paradigm.
Meet the R&D Creators
The digital electronics industry has transformed our lives in immeasurable ways is defined by the simple fact that, for 60+ years, we have benefited from exponentially more computing power, at a continually lower cost.
This fact is no longer true. For the first time in history, increased performance requires increasing costs and this coincides with an explosion in demand for more compute power driven by AI.
We're bringing expertise across three critical technology domains (AI systems design, mixed-signal CMOS circuits, and advanced networking) and a strong institutional mix (spanning academia, non-profit R&D organisations, startups and multinational companies), to pull novel ideas to prototypes and into real-world applications.
1 | Charting the Course
We’re funding two projects to develop software simulators to help the research community map the expected performance/power/cost for any future combination of algorithm, hardware, componentry, and system scale. The goal is to quantify the bottlenecks from different components in the stack, and enable agile adaptation to a fast-paced algorithms research community.
Breaking Down the Compute Graph Step by Step: A scalable and modular simulation
Aaron Zhao, Imperial College London; Luo Mai, University of Edinburgh; Robert Mullins, University of Cambridge
Heterogeneous Scale-Out Platform Simulator
James Myers, Imec
The Creator experience
What you can expect as an ARIA R&D creator
How we work
Find out more about our research model and how we fund